1. Field of the Invention
The present invention relates to a clamp circuit installed in a semiconductor integrated circuit and configured to clamp a voltage inputted to an input terminal of the semiconductor integrated circuit.
2. Description of the Related Art
Miniaturization of manufacturing process of a large scaled integrated circuit (LSI) has been accelerated in order to make faster the operating rate of the LSI and more compact the chip area thereof in recent years.
The acceleration of miniaturization causes a gate oxide of, for example, a MOS (Metal Oxide Semiconductor) device in the LSI to become increasingly thin so that it is necessary to drop a voltage applied on a gate of the MOS device for securing the lifetime thereof. The thin gate oxide also needs to prevent the applied voltage on the gate from exceeding the supply voltage as much as possible in order to avoid the deterioration of MOS device and the destruction thereof.
Using a voltage down converter to make low the supply voltage of the MOS device is effective in the drop of applied voltage on the gate thereof, and the voltage down converter is applied to an internal logic circuit of the LSI. Adding a clamp circuit between input terminals for external signals of the LSI and internal circuits thereof, or that to an exterior of the LSI is effective in the prevention of applied voltage over the supply voltage.
One of conventional structures of LSIs related to analog clamp circuits, which is applied to an ECU (Electronic Control Unit) of vehicles, is explained with reference to FIG. 5.
In the LSI shown in FIG. 5, a power supply IC (Integrated Circuit) 2 is mounted on a control substrate 1 for outputting a supply voltage VDD of 5V xc2x15% for control according to an input of battery voltage VB. A control IC 3 is mounted on the control substrate 1 to which a plurality of signals from sensors are inputted. The control IC is operative to perform various controls according to the inputted sensor signals.
A clamp circuit 4 is mounted on the control substrate 1 to be disposed to an exterior of the control IC 3.
Each of the sensor signals inputted from a connector 5 has a usually range from 0V to 5V. However, one part of terminals of the connector 5 provided for detecting whether or not signals are inputted thereto, or another part thereof connected to a faulty sensor may be subjected to the battery voltage VB up to approximately 16V.
Respective sensor signals inputted from terminals 5c and 5d are inputted through resistors R1, R3 and R2, R4 to buffer circuits 6 and 7 inside of the control IC 3. The sensor signals outputted from the buffer circuits 6 and 7 are further inputted to channels of an analog/digital converter (A/D converter), respectively.
A zener diode D1 is connected between a common connection point of the resistors R1, R3 and a grand line 8 at the exterior of the control IC 3, and a zener diode D2 is connected between a common connection point of the resistors R2, R4 and the grand line 8 at the exterior of the control IC 3. The zener diodes D1 and D2 provide the clamp circuit 4 and have zener voltages of 5.3 V, respectively.
Each of diodes D3, D4 is connected between each of input terminals of each of the buffer circuits 6, 7 and the grand line 8. Each of diodes D5, D6 is connected between each of input terminals of each of the buffer circuits 6, 7 and a control voltage line 9. These diodes D3 to D6 provide a clamp circuit 10 inside of the control IC 3.
In this structure, input voltages of the input signals to the buffer circuits 6, 7 are regulated in the range from xe2x88x92VF of approximately xe2x88x920.5 V to 5.3 V independent of the level of each of the input signals thereto.
Process, therefore, for MOS devices each having high-withstand voltage of 5V+10 %, such as 5.5 V and low-withstand voltage of xe2x88x9210%, such as xe2x88x920.5 V, that is, process for low-withstand devices can be adopted to manufacture the internal circuits including the buffer circuits 6, 7.
However, in cases where a large number of sensor signals are inputted to the control IC 3, zener diodes must be required with respect to the sensor signals, respectively, causing the area of the control substrate 1 to increase and the cost of the clamp circuits to rise.
In contrast, when removing the zener diodes D1, D2 from the clamp circuit 4, the regulation voltage of high-voltage side of the input signal becomes 5.25 V+VF, which equals to an approximately little less than 6 V, in accordance with voltage variation of 5 Vxc2x15% of the supply voltage VDD.
In this case, even when adopting the low-withstand device process with respect to the buffer circuits 6, 7, MOS devices of the buffer circuits 6, 7 are not immediately broken down, but hot carriers or slow traps are graduately generated in the MOS devices of the buffer circuits 6, 7 so that the generated hot carries or slow traps cause the threshold voltages to vary, finally making the MOS devices deviate from these original electric specs.
In order to avoid the generation of the hot carriers or the slow traps, process for MOS devices each having high-withstand voltage of 6V, in other words, process for high-withstand devices, must be adopted to manufacture the signal input portion of the LSI, causing the cost of manufacturing the LSI due to an addition of the process for high-withstand devices to be increased, and the operating rate thereof to be decreased.
Each of the clamp circuits 4 and 10 shown in FIG. 5 has a characteristic of comparatively large variation of each of the clamp voltages due to temperature changes so that, when adopting the clamp circuits 4 and 10 to an ECU for vehicles which is utilized in environments in which large temperature changes occur, it is hard to get sufficient accuracy of clamp voltages of the claim circuits 4 and 10.
The invention is made on the background of the need of the related arts.
Accordingly, it is an object of the invention to provide a clamp circuit installed in a semiconductor integrated circuit, which is capable of omitting external elements required for the operations of the clamp circuit as much as possible, and making decrease the clamp voltage variation due to temperature changes.
In order to achieve the object, according to one aspect of the present invention, there is provided a clamp circuit integrated in a semiconductor integrated circuit with an input terminal and configured to clamp a voltage inputted to the input terminal of the semiconductor integrated circuit, the clamp circuit comprising: a first transistor having a gate, a source, a drain connected to the gate and a conductivity type, the first transistor being configured to shift a target clamp voltage applied on the source by a gate-source voltage to output the shifted target clamp voltage, the gate-source voltage representing a voltage between the gate and the source of the first transistor; a buffer circuit having an output terminal and connected to the first transistor, the buffer circuit being configured to input the shifted voltage outputted from the first transistor and output a reference voltage according to the inputted shifted voltage; and a second transistor having a gate, a source, a drain and a conductivity type which is the same as the conductivity type of the first transistor, the gate being connected to the output terminal of the buffer circuit, the source being connected to the input terminal of the first transistor.
In order to achieve the object, according to another aspect of the present invention, there is provided a clamp circuit integrated in a semiconductor integrated circuit with an input terminal and configured to clamp a voltage inputted to the input terminal of the semiconductor integrated circuit, the clamp circuit comprising: a first transistor having a base, an emitter, a collector connected to the base and a type of junction, the first transistor being configured to shift a target clamp voltage applied on the emitter by a base-emitter voltage to output the shifted target clamp voltage, the base-emitter voltage representing a voltage between the base and the emitter of the first transistor; a buffer circuit having an output terminal and connected to the first transistor, the buffer circuit being configured to input the shifted voltage outputted from the first transistor and output a reference voltage according to the inputted shifted voltage; and a second transistor having a base, an emitter, a collector and a type of junction which is the same as the type of junction of the first transistor, the base being connected to the output terminal of the buffer circuit, the emitter being connected to the input terminal of the first transistor.